The Mobile Revolution: Taking it to the Next Level

By Srinivas Nori

Today our friends at ARM announced the launch of their newest processor targeted at the rapidly growing market for mid-range mobile devices. The ARM Cortex-A12 processor is expected to offer a significant performance uplift and direct upgrade path from the highly successful Cortex-A9 processor, while matching the energy-efficiency of its predecessor.

Most of the attention these days goes to the latest and greatest high-end superphones and tablets—and of course ARM has processors to serve this important segment—but the market for entry-level and mid-range smartphones is where the real growth is expected to occur in the coming years. For example, a recent report by ABI research projected that shipments of sub-$250 smartphones will grow from 259 million units in 2013 to 788 million units in 2018, at which point they will make up nearly half (46%) of the global smartphone market.

What do consumers want in an entry-level smartphone? They expect similar levels of performance and battery life as enabled by application processors for high-end smartphones, but in a more cost-effective system. Delivering this functionality is no small challenge, and it requires a tight partnership between SoC design and process technology to optimize performance, power, and cost.

ARM_GF_Timeline
Timeline of GLOBALFOUNDRIES and ARM’s relationship

We have been collaborating for years to optimize ARM processors for GLOBALFOUNDRIES leading-edge process technology. Today, in conjunction with the launch of the Cortex-A12 processor, we announced new power, performance and cost optimized POP™ IP technology offerings for the ARM Cortex-A12 and ARM Cortex-A7 processors for our 28nm-SLP High-K Metal Gate (HKMG) process technology. You can read more here about this latest milestone in our multi-year collaboration with ARM. The upshot is that this combination of ARM’s processor IP and our leading-edge process technology will enable a new level of system performance and power efficiency with the optimum economics necessary to serve the market for mid-range mobile devices. GLOBALFOUNDRIES’ 28nm-SLP process technology and associated ARM POP IP for the Cortex-A12 processor enables up to 70 percent higher performance (measured single-thread performance) and up to 2x better power efficiency in comparison to a Cortex-A9 processor using 40nm process technology. Designers can achieve even higher performance by trading off for lower power efficiency, depending on their application needs.

But of course the technology industry continues its relentless march forward, and we have no plans to stop there. We are already collaborating to optimize ARM processor IP for our next-generation 14nm-XM technology. Our 14 nm-XM offering is based on a modular technology architecture that uses a 14nm FinFET device combined with elements of GLOBALFOUNDRIES’ proven 20 nm-LPM process, which will give SoC designers the benefits of FinFET technology with reduced risk and time-to-market. The XM stands for “eXtreme Mobility,” and it is truly optimized for mobile SoC designs.

14XM_Dual-Core_Cortex-A9_PPA_Proof_Point
14XM Dual-Core Cortex-A9 PPA Proof Point. Similar results are expected for Cortex-A12

Back in February at the Common Platform Technology Forum, we announced results from the industry’s first implementation of a dual-core ARM® Cortex™-A9 processor using FinFET transistors. We found the following results for a Cortex-A9 processor implemented on 14nm-XM technology. Similar results are expected for Cortex-A12 processor implementations.

Here are the technical details:

  • High-performance, energy-efficient ARM processors implemented on 28nm-SLP typically use 12-track libraries. However at 14nm-XM FinFET technology, much higher performance and more energy-efficient ARM processors can be implemented using 9-track libraries resulting in further die-size reductions.
  • At constant power, the frequency achieved with 14nm-XM technology based implementation (using 9-track libraries) is expected to be 61% faster than the frequency achieved with 28nm-SLP technology based implementation (using 12-track libraries).
  • At constant frequency, the power consumed by 14nm-XM technology based implementation is expected to be 62% lower than the power consumed by 28nm-SLP technology based implementation.
  • The performance-power efficiency of 14nm-XM technology based implementation (expressed as DMIPs/milliwatts) is anticipated to be more than twice that of the 28nm-SLP technology based implementation, while using half the silicon area.

The mobile revolution has only just begun. We are excited to see where this dynamic industry will go next, and you can be sure we will continue collaborating with innovative partners like ARM to bring the next generation of connected devices to life.

Srinivas Nori is director, SoC innovation at GLOBALFOUNDRIES. In this role Srinivas owns the GLOBALFOUNDRIES strategy and realization for ARM ecosystem based solutions. Srinivas also oversees the exploration, identification, evaluation and collaborative offering of innovative SoC solutions.

What’s In A Name?

By Subi Kengeri

Consumers continue to demand smaller, faster and more energy-efficient electronic devices, driving the semiconductor industry to accelerate development of commercially viable chips on more advanced nodes. However, these new nodes don’t just appear by magic. It takes a great deal of careful planning to develop and deliver a process technology platform that offers competitiveness, differentiation, and manufacturability. This is the job of my team at GlobalFoundries. It always has been difficult, but the transition to 20nm and beyond presents a host of new challenges, requiring a fundamentally new approach to technology architecture and definition.

Over the past few nodes, SoC designers have grown accustomed to a roughly 30% reduction in die cost from node to node. But 20nm is the first node on which foundries introduced true double-patterning lithography, which increases manufacturing costs, largely dependent on the target application. So there has to be something else to prompt customers to adopt this new node. For example, it is critical that a technology platform deliver SoC product value and designability, and has to be optimized for the customer’s target application. At 20nm, we really began looking at the product level value for customers, which we define in terms of the optimum combination of performance, power and cost (PPC), in addition to other customer care-abouts.

We took this to a whole new level with our recently launched 14nm-XM offering. Once we had optimized PPC for our 20nm planar SoC offering, we looked at what it means to incorporate 3D FinFETs on the next node. Going from planar to FinFET gives us a step jump in performance and power, but minimal benefit in die size because we chose to use the fully optimzed middle and backend of line from 20nm-LPM. The key was to architect 14nm-XM to ensure the performance and power advantages outweigh the lack of area improvement and to ease designability on the first generation FinFET offering. Leveraging the 20nm-LPM competitive density advantages and using the most optimal 3D fin structure, we expect to get back on the historical 60% to 70% SoC PPC improvement trajectory. We also expect to see a big benefit in time-to-volume (on a node to node basis) because we will leverage key technology modules and PDKs from 20nm-LPM, which we believe will allow our customers to design concurrently and accelerate our FinFET high volume ramp by about one year.

Image

But one question I often get asked is, ‘Why do we call it a 14nm technology if it relies so much on 20nm?’ First of all, we are using a true 14nm-class FinFET as the front-end device, which qualifies it as a 14nm technology. But in reality the naming of nodes has become somewhat arbitrary over the past several nodes. A node used to be named based on the smallest transistor feature size, which was typically the channel length. But channel length scaling stopped at about 45nm, so the industry does not actually have a 28nm gate in a 28nm technology. Secondly, the point of moving to a new node is the delivery of value to the customer. They need to see a SoC level product value, which really translates to the PPC, and 14nm-XM offers a full node value. As long as customers see at least this level of value, they frankly don’t care what the technology is called or what is inside.

Now we need to find a way to deliver this same product level value at 10nm. The whole industry has quite a few challenges going to 10nm. FinFETs are scalable and will have a long life, but we will have already realized the performance and power value from the front-end device with 14nm-XM. We don’t expect extreme ultraviolet (EUV) lithography will be ready, at least not at the beginning of the node, which means we will have more layers that require multiple patterning and therefore significant cost increases. We will need to find other ways to provide performance and power benefits to deliver a total PPC to stay on the SoC value trajectory. We have been working on this and 7nm technologies for several years and we are very close to nailing down a competitive 10nm technology architecture. We are running 10nm devices in silicon and I am confident we will deliver the value our customers have come to expect.

For more detail on this topic, check out the recent interview with SemiMD’s Mark LaPedus, where we talk about FinFETs, EUV, and Moore’s Law.

Subramani “Subi” Kengeri is vice president of advanced technology architecture at GLOBALFOUNDRIES.

This post also appeared on Chip Design Magazine

Reshaping the Foundry Industry: Welcome to Foundry 2.0

CEO Ajit Manocha lays out winning strategy for nation’s comeback at Nikkei Electronics’ World Semiconductor Summit

GLOBALFOUNDRIES CEO Ajit Manocha spoke to a crowd of more than 200 high-ranking executives from the Japanese semiconductor industry last week at the Nikkei Electronics’ World Semiconductor Industry Summit 2013 in Tokyo. During Manocha’s presentation titled, “Reshaping the Foundry Industry: Welcome to Foundry 2.0,” he outlined the evolution and future of the foundry model, the technical and business drivers reshaping the landscape and what it will take for Japanese IDM companies to move forward. Manocha urged Japanese companies to embrace the fabless model and revise their perspective on previous paradigms.

GLOBALFOUNDRIES is committed to the idea that future success in the semiconductor industry is dependent on joint development at the technology definition level, early engagement at the architectural stage and leveraging a more integrated and cooperative ecosystem. The same theme was very present in Manocha’s speech as he emphasized that the idea that Japan’s resurgence into the semiconductor industry can be fueled collaborative device partnerships.

GLOBALFOUNDRIES recently demonstrated its commitment to collaboration at The Common Platform Technology Forum 2013, where we made a number of joint announcements with our partners. Among those collaborations include Rambus, Synopsys, Adapteva and Cyclos Semiconductor – all of which will mutually benefit GLOBALFOUNDRIES and our partners, but more importantly our customers.

You can watch Manocha’s full speech online on our YouTube channel. Important highlights include:

  • The old foundry model will no longer work with due to a slower rate of change, and inflexible methods and systems which are now required to become flexible (23:33)
  • Our vision for 2020 includes homogeneous alliances as well as heterogeneous alliances between foundries, the airline industry, banking industry, semiconductors and the biomedical field (24:53)
  • GLOBALFOUNDRIES’ acceleration of growth, viewed as a timeline (31:36):
    • From 2007 to 2012, we developed the 65-, 45-, 32- and 28nm designs
    • From 2013 to 2017, we have plans to break into the 20-, 14-, 10- and finally the 7nm design

Common Technology, Uncommon Solutions

common platformBy Mike Noonen

Collaboration has become a well-worn buzzword in our industry in recent years, and for good reason. The scale and complexity of the challenges we collectively face can only be addressed by working together across the entire semiconductor ecosystem. But while many companies are just giving lip service to the concept of collaboration, it has been a part of our DNA at GLOBALFOUNDRIES since our inception.

One of our most important partnerships is in the form of the Common Platform alliance, a groundbreaking collaboration with IBM and Samsung—two of the world’s foremost technology companies—to address the needs of semiconductor manufacturing by providing access to leading-edge CMOS process technologies and extensive enablement support and services. Together we are continuing to redefine the landscape of the semiconductor industry, and the fruits of this partnership will be on display next week at the 2013 Common Platform Technology Forum, which will be held on Tuesday, February 5 at the Santa Clara Convention Center.

The theme of this year’s forum is “Real Collaboration = Big Business.” While we will still be providing a deep look into the underlying technologies offered by the alliance, we also want to demonstrate the impressive business momentum that’s been achieved as a byproduct of this collaboration. 2012 was a particularly strong year, with members of the Common Platform seeing significant growth and taking over both the #2 and #3 spots in the worldwide foundry rankings. Research firm IC Insights recently released its projections for the top 20 leading semiconductor suppliers in 2012, and GLOBALFOUNDRIES jumped six spots to break into the top 20 for the first time. IC Insights projected our 2012 revenue to grow 31% over 2011, which would make us the fastest growing semiconductor company in the world. Similarly, IC Insights’ 2012 foundry rankings saw Samsung make a rapid rise to #3 in the foundry, with a near doubling of foundry revenue for two years in a row.

The forum also will showcase the latest technological advances being delivered to the world’s leading electronics companies. Attendees will see and hear firsthand how the combined expertise of our partners is addressing the most demanding IC design and manufacturing challenges. Our collaborative research and innovative technology development have resulted in an accelerated roadmap and rapid customer adoption, and we’ll touch upon these key highlights:

  • Leading-edge process technologies at 32/28-, 20-, 14-nanometer, and beyond
  • Advanced innovations such as FinFet, design & technology co-optimization, and double patterning
  • A peek into the future of next-generation device innovations being researched: silicon nanowires, carbon nanotubes, and 3D device structures
  • A showcase of our ecosystem partners and Common Platform design, enablement, and implementation offerings in our Partner Pavilion

During the morning session, attendees will have the opportunity to hear keynotes from senior leaders at IBM, Samsung, and GLOBALFOUNDRIES, as well as a special keynote from Dr. Dipesh Patel, Executive Vice President and General Manager of the Physical IP Division at ARM. Dr. Patel will talk about the importance of “partnering for innovation to drive diversity.” Mobile computing is fueling the market demand for diversity, innovation, and expansion of the semiconductor industry, but the challenges being faced by system and SoC designers to meet these requirements in terms of performance, power efficiency, and time-to-market continue to grow in light of advanced manufacturing technologies. Dr. Patel will discuss the importance of a strong ecosystem to deliver the right product on time for commercial success, and why “Real Collaboration” on advanced process technology is a necessary and critical ingredient to address these challenges.

If you aren’t able to attend Tuesday’s event in person, please consider tuning in online via the live webcast, which will also be archived after the event. Details can be found at this link: http://www.commonplatform.com/tf2013

Mike Noonen is Executive Vice President, Worldwide Marketing and Sales, for GLOBALFOUNDRIES. In this role, he is responsible for global customer relationships as well as all marketing, sales, customer engineering and quality functions.

GLOBALFOUNDRIES’ Alexie Lee Recognized for Excellence in Manufacturing

Earlier this week, the Manufacturing Institute, the Society of Manufacturing Engineers, University of Phoenix and Deloitte named GLOBALFOUNDRIES’ Alexie Lee one of the first recipients of their Women in Manufacturing STEP (Science, Technology, Engineering and Production) Awards. Honoring women who have demonstrated excellence and leadership in their careers, the announcement highlights Alexie’s achievements in manufacturing through her positive impact on both GLOBALFOUNDRIES and the industry as a whole.

Alexie Lee

In her role as General Counsel and Executive Vice President of Legal and Corporate Affairs, Alexie is responsible for litigation, intellectual property and corporate matters. Additionally, Alexie oversees worldwide corporate communications, government relations and corporate risk management and sustainability, while providing direction and counsel to the CEO, the Board of Directors and other top corporate leaders. GLOBALFOUDRIES’ growth from a one-facility operation to a company with 7 production facilities worldwide can be attributed in part to her actions and strong understanding of the importance of manufacturing to the entire economy. She adds, “I am excited about being involved in the most advanced of advanced manufacturing.  Not only is our industry vital to our nation’s strength, our products drive improvements, at times dramatic, in all our lives.”

GLOBALFOUNDRIES CEO, Ajit Manocha said, “Since helping to launch GLOBALFOUNDRIES in 2009, Alexie has exhibited a tremendous track record of execution and collaboration, helping to propel our company as one of the fastest-growing semiconductor companies in the world. Her leadership is helping GLOBALFOUNDRIES create thousands of new advanced manufacturing jobs in the U.S., and expand the high-tech manufacturing capabilities that will continue to pave the way for long-term economic growth in the U.S. We thank Alexie for her hard work and dedication and we are so proud to see her recognized with this prestigious award.”

The STEP Ahead initiative was launched to examine and promote the role of women in the manufacturing industry through recognition, research and best practices for attracting, advancing, and retaining strong female talent. A total of 122 women were honored this first year, representing a variety of companies at all levels of their manufacturing organization from the factory floor to the C-suite. Award organizers hope that by telling the stories of these women, they can help inspire the next-generation of talent to pursue careers in the industry.  The STEP Awards are also meant to empower honorees to lead in their companies, communities and networks on the importance of manufacturing and issues related to attracting, advancing and retaining strong manufacturing talent.

“The STEP Ahead initiative was founded to change perceptions of the manufacturing industry and create new opportunities for women in the sector,” said Latondra Newton, group vice president at Toyota Motor North America, Inc. and chairwoman of the STEP Ahead initiative. “This initiative is the call for action to transform the face of today’s manufacturing talent and ensure that women can contribute to the future of this industry.”

On February 5th, Alexie will join the other award recipients for a reception in Washington, D.C. where the STEP Awards program will highlight each honoree’s story, including their leadership and accomplishments in manufacturing.

GLOBALFOUNDRIES to Build Leading-Edge R&D Center on Fab 8 Campus

Aerial view of Fab 8 (rendering)

On January 8th, GLOBALFOUNDRIES announced it will soon begin construction on a new research and development facility at the Fab 8 campus.  Featuring more than a half million square feet of flexible space to support a range of technology development and manufacturing activities, the new Technology Development Center (TDC) will play a key role in the company’s strategy to develop innovative semiconductor solutions allowing customers to compete at the leading edge of technology.

TDC site plan

“As the industry shifts from the PC era to a market focused on mobile devices, we have seen increasingly strong interest from customers in migrating to advanced nodes on an accelerated schedule,” said GLOBALFOUNDRIES CEO Ajit Manocha. “To help facilitate this migration, we are making significant investments in strengthening our technology leadership, including growing our workforce and adding new capabilities to make Fab 8 the hub of our global technology operations.  The new TDC will help us bridge between the lab and the fab by taking research conducted with partners and further developing the technologies to make them ready for volume manufacturing.”

The TDC will house a variety of semiconductor development and manufacturing spaces to support the transition to new technology nodes, as well as the development of innovative capabilities to deliver value to customers beyond the traditional approach of shrinking transistors.

The overarching goal of the TDC is to provide a collaborative space to develop end-to-end solutions covering the full spectrum of silicon technology, from new interconnect and packaging technologies that enable three-dimensional (3D) stacking of chips to leading-edge photomasks for Extreme Ultraviolet (EUV) lithography and everything in between. The TDC will also house important post-production capabilities, including ETest, Bump and Probe, which are increasingly needed at the foundry location for fast yield feedback and to support customer business models.

The Fab 8 campus is an ideal home for the company’s leading-edge technology development activities.  The proximity of the IBM Joint Development Alliance activities in East Fishkill and the College of Nanoscale Science and Engineering (CNSE) at the University of Albany, combined with the growing presence of technology development personnel on the Fab 8 campus, have helped make New York’s “Tech Valley” a global center for next-generation technologies.

Renderings of Fab 8 campus with TDC renderings

“This significant expansion demonstrates that the investments we have made in nanotechnology research across New York State are producing the intended return— the creation of high-paying jobs and generation of economic growth that is essential to rebuilding our state,” said New York Governor Andrew M. Cuomo.  “New York has become the world’s hub for advanced semiconductor research and now, the Technology Development Center will further help ensure the innovations developed in New York, in collaboration with our research institutions, are manufactured in New York.”

Speaking about the announcement, CNSE Senior Vice President and CEO Dr. Alain Kaloyeros said, “The expansion of GLOBALFOUNDRIES’ advanced technology and manufacturing capabilities, supported by new investments and location of new high-tech research and development jobs at the College of Nanoscale Science and engineering, will fuel exciting opportunities for both residents and businesses across New York State, in accordance with Governor Cuomo ‘New York Open for Business’ strategy, and continue to pave the way for long-term economic growth and prosperity catalyzed by computer chip innovations.”

The company plans to begin construction in early 2013 with completion targeted for late 2014.  Since breaking ground on Fab 8 in 2009, GLOBALFOUNDRIES has created approximately 2,000 new direct jobs and that number is expected to grow by another 1,000 employees for a total of about 3,000 new jobs by the end of 2014.   

Quick Facts about the TDC

  • Three-level building with approximately 550,000 gross square feet of varying occupancy types
  • Approximately 90,000 square feet of flexible cleanroom space
  • Approximately 108,000 square feet of clean space to support a range of technology development and manufacturing activities
  • The additional investment in the TDC will increase the total capital investment for the Fab 8 campus to approximately $8.5 billion

For more information on the TDC, check out these resources and articles 

“Layer Cakes” and Mobile Devices – Yes, There’s a Connection

By Dr. John Heinlein

There’s no denying the pervasiveness of mobile devices and mobile communications technologies. These applications are obviously changing how we communicate and share information, but also increasingly how we do business.  And consumers keep expecting more from their mobile devices.  Today, the performance and capability in high-end smartphones and certainly tablet computers are getting on a par with notebook computers. Consumers who previously didn’t know or care about technical specifications are being barraged with milliwatts, gigahertz, and nanometers.  Form factors of devices are becoming more and more critical to differentiating a device, where new devices are measured in millimeters and grams compared to prior generations.  And of course, there is the pervasive need for more battery life.  The irony is that making devices smaller and thinner means less volume (and mass) for the lithium ion-based chemical batteries that are today’s standard energy carrier. Consumers still expect their devices to do more and also last longer when running, as well as when they are on stand-by.

These increasing expectations for mobile present opportunities as well as technical challenges that we in the semiconductor industry must address.

My wife will attest that I have an insatiable sweet tooth, and so it’s not surprising that I equate this problem with a layer cake, featuring many layers (chocolate, thank you very much).  Like a well-formed layer cake, the problem of delivering leading, next-generation mobile devices is not solved through any one component or technology. It takes a solution with all the layers of the stack working together.

At the highest level, the ARM Connected Community features over 970 partners who deliver value-added capabilities to the ARM partnership.  These providers span applications, middleware, tools, IP blocks, design services, and a whole host of other capabilities, and the breadth of the ecosystem supports the richness of capabilities that enables the mobile devices we love.

ARM itself focuses our efforts on a range of technologies that are important to the middle layers of the cake.  ARM delivers our industry-leading, energy-efficient Cortex™ processors and Mali™ graphics processors, and we continue to lead the way with continued innovation.  We recently rolled out our unique big.LITTLE technology, which gives the best of both worlds of high performance and energy efficiency.  We provide CoreLink™ system IP that connects the system together and increases performance and capabilities for sharing information across devices.  And finally we deliver Artisan® physical IP that helps designers implement these designs for manufacturing.

The lowest level of the cake involves realizing these conceptual designs into actual silicon chips that power the broad array of mobile devices. This job falls to semiconductor foundries like GLOBALFOUNDRIES, which has partnered with ARM for many years on mobile innovation. The foundry ecosystem provides a proven manufacturing solution for fabless companies, enabling the amazing growth and diversity of devices in the marketplace today.  Through this solution, the industry is delivering high-volume 28nm solutions in the market place and driving rapidly towards tapeouts of 20nm devices next year.  GLOBALFOUNDRIES, for its part, is investing heavily in its 20nm-LPM process technology, which delivers a fully scaled metallization compared to the 28nm node.  While often the focus in the media is on transistor performance, scaling the metal is critically important as well, as it drives area improvements, cost reduction and power reduction.

With GLOBALFOUNDRIES’ recent announcement of its 14nm-XM technology, the company is going beyond the 20nm node and looking to the future, and I for one think its approach is pragmatic.  It’s critical that the industry continue the pace of innovation and deliver the next wave of transistor capabilities for production in the 2014 time frame.  The growing consensus is that devices beyond 20nm will be based on a FinFET transistor, a 3D device where the current flow can be more effectively controlled using a gate on both sides of the conducting channel.

GLOBALFOUNDRIES has invested in R&D on FinFET devices for years now and it intends to roll out its FinFET-based 14nm-XM (for “eXtreme Mobility”) technology in 2013, targeting production volume in 2014.  This process technology is projected to provide significant scaling and improvement in energy-efficiency compared to previous nodes, and has the potential to extend the kinds of scaling that we have enjoyed from Moore’s Law for so many years. Given the complexity of rolling out a new device technology, the approach leverages the metal solution from 20nm-LPM. This reduces one of the major risk factors in rolling out a new technology, since metal scaling is also a key challenge for manufacturability.

GLOBALFOUNDRIES has also committed to collaborating with ARM to jointly optimize this process technology specifically for next-generation ARM processors and graphics for the mobile market. This joint optimization is delivered in part through the ARM POP™ IP product line for chip optimization and risk reduction, is a key element in assuring customers get to market quickly with new designs.  By delivering POP IP for GLOBALFOUNDRIES 20nm-LPM and 14nm-XM technologies, we can assure the pace of innovation continues into the future.

We are excited that the foundry industry is responding with aggressive technologies that will help drive the next generation of manufacturing and look forward to the exciting new products that this technology will enable.

Dr. John Heinlein is vice president of marketing for the Physical IP Division at ARM

28nm-SLP technology – The Superior Low Power, GHz Class Mobile Solution

By Kelvin Low

In my previous blog post, I highlighted our collaborative engagement with Adapteva as a key factor in helping them deliver their new 64-core Epiphany-4 microprocessor chip. Today I want to talk about the second key ingredient in enabling their success: the unique features of our 28nm-SLP technology.

As the Product Marketing lead for our leading edge technologies, I am always intrigued by some of the discussion threads in the industry, especially during the introduction of the 28nm roadmap. We have done extensive study, gathering inputs from our customers, the design community, market segment experts and end product companies. The various inputs of requirements that the industry wanted of a 28nm technology node can be summarized in a few bullet points:

  • At least 35% performance scaling from prior low power node.
  • Leakage and power reduction of at least 40% from prior node.
  • 50% area scaling or 2x more device density, a critical need for increased feature integration on the SoC.
  • And of course fastest time to design and time to market.

We came up with the perfect solution – 28nm-SLP. The result of our collaboration with our partners in the Joint Development Alliance (JDA), the technology is implemented using our unique high-k metal gate (HKMG) Gate First integration. Why?

1.  HKMG

Gate oxide thickness scaling was reaching its limits at the 40nm node. We had seen significant product leakage issues and there had to be design workarounds to bring the leakages down to acceptable levels, but this results in inefficient designs leading to product area increase.   As we scale down to 28nm, there’s a need to maintain good short channel control and to do this, we have to push the electrical gate dielectric thinner.  This is tricky.  Studies have shown that if we thin down the gate dielectric material used in 40nm, which is Poly-Silicon OxyNitride (PolySiON), gate leakage will increase to unacceptable levels.  So, high-k dielectric was introduced.   Metal gate was included as part of the overall integration to achieve the right work function for the transistors.  The result – product performance improvements of more than 35% and 40% lower power than 40nm.

2.  Gate First Integration

HKMG can be realized with two main approaches: Gate First or Gate Last implementation.  While it is well known that Intel employed the Gate Last HKMG approached for their 45nm CPU technology, GLOBALFOUNDRIES concluded that this was not the most optimum approach for our customers. We (and our JDA partners) chose the Gate First integration at 32/28nm as it provided clear benefits in the following areas:

  • Simpler process integration, which results in a less complex and cost effective technology.
  • No need for complex (and expensive) stress engineering for our 28nm-SLP (e.g. no embedded SiGe source/drain modules) in contrast to something like a ‘low power’ PolySiON or high performance HKMG alternatives.
  • None of the design restrictions associated with a Gate Last implementation.  We allow dual gate orientation, poly jogs and have simpler analog related design rules.  Through various designers’ feedback, it was conclusive that our technology results in a 10-15% smaller die size, easy analog implementation and easier to port key complex IPs from the prior node (vs. a PolySiON or Gate Last HKMG alternatives)

The net result: our technology provides a 100% increase in gate density and easier implementation of IPs allows for faster (and lower risk) design turn around.

There are many more benefits that I could share, but the most important proof point of our technology is where we are today in terms of volume production. Silencing the skeptics that HKMG Gate First was not a manufacturable technology, we have already shipped more than 350,000 wafers of HKMG today – the largest number of wafers among all pure play foundries. End products are already available on the shelf and have shown superior performance from benchmarking data.

In the relentless drive to move into the next leading edge node, GLOBALFOUNDRIES has been working with our lead partners at the next nodes (20nm and 14nm) for more than 18 months. New technology elements and innovations like double patterning, middle of line (MOL) modules, and FinFET transistors are complex elements that will be required allow Moore’s law scaling to continue. Again, we are collaborating with our customers and design ecosystem partners to devise the best solution for the industry. Only by early and close partnerships will we have win-win solutions with our customers and partners.

Kelvin Low is Product Marketing Deputy Director for GLOBALFOUNDRIES, responsible to define GLOBALFOUNDRIES leading edge technology roadmaps and product solutions. He is also an active member of the Joint Development Alliance where he is the marketing lead providing key market inputs in shaping the next technology nodes.

Enabling Innovation on Leading Edge Technology

By Kelvin Low

It’s always great to see a customer celebrate their product success, especially when it’s developed based on a GLOBALFOUNDRIES technology.  Recently, one of our early lead partners, Adapteva, announced sampling of their 28nm 64-core Epiphany-4 microprocessor chip. This chip is designed on our 28nm-SLP technology which offers the ideal balance of low power, GHz class performance and optimum cost point. I will not detail the technical results of the chip but will share a quote by Andreas Olofsson, CEO of Adapteva, in the recent company’s press release:

“The Epiphany efficiency breakthrough will enable significant savings in total cost of ownership for high performance computing and will enable server level performance in mobile devices such as smart-phones and tablets. . . . effectively offering over 50 GHz of achievable programmable performance while consuming less than 2 Watts”

The ability to achieve this high performance point and still maintain mobile class leakage does not come by ‘magic’. I attribute the joint success to two key factors:

  1. Early collaboration between Adapteva and GLOBALFOUNDRIES.
  2. The low leakage, GHz attributes of our 28nm-SLP technology.

Early collaboration with our customers

GLOBALFOUNDRIES is transforming the foundry engagement model. While some in the industry may claim that “the foundry-fabless model is dead,” we are seeing the exact opposite! We are leading the transformation to a new model of customer-foundry relations. Early collaboration with customers in many aspects is necessary for a long-term, mutually successful relationship. To use Adapteva as an example, GLOBALFOUNDRIES engineers started engaging Adapteva’s design teams back in 2010, which is two years prior to product launch. During the initial engagement phase, both teams rigorously discussed requirements and exchanged ideas in order to meet the stringent product leakage requirements while scaling the high performance needs from the previous generation. Time-to-market was obviously a priority, and it was essential for Adapteva to work on a 28nm technology that allows fast porting of their key IP blocks (from the prior node).

Our 28nm-SLP technology was the ideal fit for Adapteva, because it offers a combination of GHz class performance and low leakage to cover the  mobile segment, as well as the critical time-to-market advantage that they need. GLOBALFOUNDRIES also works with our design ecosystem partners to enable design IPs on our 28nm platforms. These range from building blocks like standard cells, memory compilers to more complex IP blocks like USB2/3, DDR, PCI-Express and other high speed interfaces. Early access to the technology as well as design building blocks helped our customer accelerate their design cycle time.

The relationship with Adapteva is a great example of our initiative to transform the foundry business model, which we are calling the Collaborative Device Manufacturing (CDM). In my next blog post, I will talk a bit more about the second key factor that helped enable Adapteva’s success: how we built a superior low power, GHz class mobile solution in our 28nm-SLP technology.

Kelvin Low is Product Marketing Deputy Director for GLOBALFOUNDRIES, responsible to define GLOBALFOUNDRIES leading edge technology roadmaps and product solutions.  He is also an active member of the Joint Development Alliance where he is the marketing lead providing key market inputs in shaping the next technology nodes.

Innovation in Design Rules Verification Keeps Scaling on Track

By Mojy Chian

There is an interesting dynamic that occurs in the semiconductor industry when we talk about process evolution, roadmaps and generally attempt to peer into the future. First, we routinely scare ourselves by declaring that scaling can’t continue and that Moore’s Law is dead (a declaration that has happened more often than the famously exaggerated rumors of Mark Twain’s death). Then, we unfailingly impress ourselves by coming up with solutions and workarounds to the show-stopping challenge of the day. Indeed, there has been a remarkable and consistent track record of innovation to keep things on track, even when it appears the end is surely upon us.

But this time we are really serious – at 20nm, the end is near! Ok, maybe not THE end, but for sure there are some obvious things that need to change if we are to keep our record of continuous technical conquest intact. And, as with most things in this era, collaboration is the key.

Mojy Chian explains the role DFM has in keeping scaling on track.

Sure there are lots of really innovative approaches and exotic technologies being bandied about that hold the potential to keep Moore’s Law chugging along well into the future. But ironically, it’s something of an ‘old’ technology that holds significant potential to address the current issues. Design for manufacturing (DFM) has been around for a long time, most typically as a design-enabling tool delivered by EDA companies to help IC designers understand and deal with manufacturers’ geometrical design rules.  This obviously requires close interaction with the EDA people and the foundries so that design rules are accurate and practical. Literally, these are tools that guide designers with a set of geometrical constraints, necessary to guarantee yield, defined over polygonal shapes and edges in the layout. Traditionally, these design rules are binary – this works, this does not.

But something funny happened on our way past 28nm. The Y word – yield – started becoming one of the, if not the, most important factor in successful IC design. This is because of the intrinsic relationship between yield and the complexity of physical design (and the associated challenges of process-related effects).

In the past, a designer only had two primary options for identifying DFM issues: run accurate but computationally intensive simulations based on numerical algorithms, or rely on metrology measurements directly from the fab. Attempts have been made to improve upon standard DRC with additional rules, but these approaches have had mixed success. For example, some have proposed the use of restrictive design rules that only allow highly regular structures for layout, avoiding problematic two-dimensional geometries altogether. The potential drawback is that designers cannot effectively optimize their circuits to meet application requirements with overly constrained design rules.

So the manufacturers got back together with the EDA suppliers and thought about how to solve the problem. “We need to build on what we have achieved with DRC,” we agreed. “We need more.” So in our infinite wisdom, we came up with something called DRC+. The lack of creativity in the name, however, belies the innovation behind it, which is backed by several patents and reinforces the fact that GLOBALFOUNDRIES innovates in ways beyond just manufacturing process technology.

The concept we are moving towards is the reduction in the number of trade-off decisions a designer needs to make. By providing a tool that will notify the user if a forbidden shape has been used, the designer can be guided more efficiently. In addition, things need to be visually intuitive –  a picture is worth of a thousand words, even in IC design. Such a solution requires tight collaboration between the foundry, which supplies a library of yield critical patterns; EDA providers, which supply ultra-fast pattern-matching tools; and the IC design community itself which provides valuable input on design methodologies and real-world needs.

Pattern-based methodology takes hold

In a nutshell. DFM and design rule checking need to move to a pattern-based approach to provide more visibility into variability issues. Traditional DRC is shape and edge proximity based.  On top of that, we need 2D shape-based pattern-matching physical verification.

As a result, our DRC+ takes a different approach than earlier generations of DRC. Instead of restricting the flexibility of designers, the technique augments standard DRC by applying rapid two-dimensional shape-based pattern matching to identify problematic configurations that could be difficult to manufacture.

Our DRC+ platform includes a silicon verified library of “bad” patterns in a database which can be identified quickly in layout, allowing the designer to fix them. This is an on-going incremental process rather than just occurring at the end of the complete design cycle.

Thus, pattern matching with DRC+ introduces process-awareness earlier in the design process, a concept that is at the basis of the collaborative DFM platform from GLOBALFOUNDRIES.

Two rule-based flows are also part of our DFM platform. The first is yield analysis and scoring, in the form of an equation-based tool to help designers quickly analyze their design for usage of recommended rules, and prioritize fixes for the highest impact violations. The second is an automated yield enhancement “layout-fix” application, which applies recommendations without impacting overall design area.

The net result is improved variability management without sacrifices in design performance or significant impact on design productivity (DRC+ is over 10,000 times faster than printability simulation, and its detection and fixing adds very little to the overall routing runtime).

DFM is something of a broad catch-all term for a number of steps and issues involved ensuring a complex IC design can be manufactured and done in a way that is cost-effective and timely. Design rule checking is just one aspect of it, but a critical one for sure. We are proud of the innovation GLOBALFOUNDRIES continues to demonstrate in many areas, including design enablement technologies like our DRC+. In future posts I’ll explore other ideas for improving how manufacturing issues can be brought more tightly into the design process, including a concept we call Design Enabled Manufacturing (DEM). Stay tuned.

Mojy Chian is senior vice president, design enablement at GLOBALFOUNDRIES. He is responsible for global design enablement, services, and solutions and is the primary technical customer interface for the company.