What’s In A Name?

By Subi Kengeri

Consumers continue to demand smaller, faster and more energy-efficient electronic devices, driving the semiconductor industry to accelerate development of commercially viable chips on more advanced nodes. However, these new nodes don’t just appear by magic. It takes a great deal of careful planning to develop and deliver a process technology platform that offers competitiveness, differentiation, and manufacturability. This is the job of my team at GlobalFoundries. It always has been difficult, but the transition to 20nm and beyond presents a host of new challenges, requiring a fundamentally new approach to technology architecture and definition.

Over the past few nodes, SoC designers have grown accustomed to a roughly 30% reduction in die cost from node to node. But 20nm is the first node on which foundries introduced true double-patterning lithography, which increases manufacturing costs, largely dependent on the target application. So there has to be something else to prompt customers to adopt this new node. For example, it is critical that a technology platform deliver SoC product value and designability, and has to be optimized for the customer’s target application. At 20nm, we really began looking at the product level value for customers, which we define in terms of the optimum combination of performance, power and cost (PPC), in addition to other customer care-abouts.

We took this to a whole new level with our recently launched 14nm-XM offering. Once we had optimized PPC for our 20nm planar SoC offering, we looked at what it means to incorporate 3D FinFETs on the next node. Going from planar to FinFET gives us a step jump in performance and power, but minimal benefit in die size because we chose to use the fully optimzed middle and backend of line from 20nm-LPM. The key was to architect 14nm-XM to ensure the performance and power advantages outweigh the lack of area improvement and to ease designability on the first generation FinFET offering. Leveraging the 20nm-LPM competitive density advantages and using the most optimal 3D fin structure, we expect to get back on the historical 60% to 70% SoC PPC improvement trajectory. We also expect to see a big benefit in time-to-volume (on a node to node basis) because we will leverage key technology modules and PDKs from 20nm-LPM, which we believe will allow our customers to design concurrently and accelerate our FinFET high volume ramp by about one year.

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But one question I often get asked is, ‘Why do we call it a 14nm technology if it relies so much on 20nm?’ First of all, we are using a true 14nm-class FinFET as the front-end device, which qualifies it as a 14nm technology. But in reality the naming of nodes has become somewhat arbitrary over the past several nodes. A node used to be named based on the smallest transistor feature size, which was typically the channel length. But channel length scaling stopped at about 45nm, so the industry does not actually have a 28nm gate in a 28nm technology. Secondly, the point of moving to a new node is the delivery of value to the customer. They need to see a SoC level product value, which really translates to the PPC, and 14nm-XM offers a full node value. As long as customers see at least this level of value, they frankly don’t care what the technology is called or what is inside.

Now we need to find a way to deliver this same product level value at 10nm. The whole industry has quite a few challenges going to 10nm. FinFETs are scalable and will have a long life, but we will have already realized the performance and power value from the front-end device with 14nm-XM. We don’t expect extreme ultraviolet (EUV) lithography will be ready, at least not at the beginning of the node, which means we will have more layers that require multiple patterning and therefore significant cost increases. We will need to find other ways to provide performance and power benefits to deliver a total PPC to stay on the SoC value trajectory. We have been working on this and 7nm technologies for several years and we are very close to nailing down a competitive 10nm technology architecture. We are running 10nm devices in silicon and I am confident we will deliver the value our customers have come to expect.

For more detail on this topic, check out the recent interview with SemiMD’s Mark LaPedus, where we talk about FinFETs, EUV, and Moore’s Law.

Subramani “Subi” Kengeri is vice president of advanced technology architecture at GLOBALFOUNDRIES.

This post also appeared on Chip Design Magazine

GLOBALFOUNDRIES Announces Extension to Fab 8, Adding More Space and Hundreds of New Jobs

On July 24, 2012, the third anniversary of the Fab 8 groundbreaking, GLOBALFOUNDRIES announced it is moving forward with the final construction of the extension of Module 1 at the Malta, N.Y. campus. The project will add 90,000 square feet of manufacturing capacity, bringing the total capacity for Fab 8 Module 1 to 300,000 square feet. Construction will begin in August and work is expected to be completed in December 2013.

The decision to move forward with the extension comes as a result of increased demand from customers, especially at the 28nm node. Extending the Fab 8 cleanroom is expected to enable the Fab 8 capacity to reach approximately 60,000 wafers per month and it will increase the capital budget by approximately $2.3 billion, taking the total capital budget from $4.6 billion to approximately $6.9 billion, once tools and equipment are installed.

GLOBALFOUNDRIES began construction on Fab 8 in July 2009 and began moving people and equipment into the facility in mid-2011. Initial wafer starts began earlier this year and the facility is on track to begin risk production by the end of the year, with volume production in early 2013.

“By continuing to expand our investment in the project, GLOBALFOUNDRIES is delivering more options to our global customers, while helping to redefine upstate New York as a premier hub of the global semiconductor industry, creating thousands of new advanced manufacturing jobs, and contributing billions of dollars to the regional economy,” said Eric Choh, vice president and general manager of Fab 8.

Since breaking ground on Fab 8 in 2009, GLOBALFOUNDRIES has created more than 1,500 new direct jobs, in addition to 4,300 construction-related jobs. The project is the largest private Project Labor Agreement in history, generating hundreds of millions of dollars of economic development throughout upstate New York during the worst economic downturn since the Great Depression.

Enabling the Next Generation of Packaging Innovation

Today we announced a significant milestone on the road to enabling 3D stacking of chips for next-generation mobile and consumer applications. At our Fab 8 campus in Saratoga County, NY, we recently began installation of a special set of production tools to create Through-Silicon Vias (TSVs) in semiconductor wafers processed on our leading-edge 20nm technology platform.

In the following video, we sat down with David McCann, senior director of packaging R&D, to get a better sense of the significance of this announcement, as well as GLOBALFOUNDRIES’ overarching strategy to enable next-generation packaging technologies.

What a Quarter Million Wafers Really Means To Our Customers

An aerial view of Fab 1 in Dresden, Germany

Yesterday we announced a significant milestone at Fab 1 in Dresden, Germany—the shipment of 250,000 wafers based on 32nm High-k Metal Gate (HKMG) technology. A quarter million wafers is a lot of silicon. If all of these wafers were laid side-by-side the trail would run for 47 miles, or about half the distance from Dresden to Prague, the largest city in the Czech Republic.

But of course our customers don’t sell wafers—they sell computer chips. So what does this milestone mean to our customers?

Our largest 32nm customer is AMD. They make several products using this process technology, including Accelerated Processing Units (APUs) for notebooks and desktops, and high-performance processors for servers and workstations. AMD’s president and CEO Rory Read summed up the news from their perspective:

In just one quarter, we were able to see more than a doubling of yields on 32nm, allowing us to exit 2011 having exceeded our 32nm product shipment requirements. Based on this successful ramp of 32nm HKMG, we are committed to moving ahead on 28nm with GLOBALFOUNDRIES.

We have been very open about the challenges we faced at the beginning of the 32nm ramp in Fab 1. Not only were we moving to a new technology node and manufacturing the foundry industry’s first HKMG product, but the transition also represented our first integration of a CPU and GPU on the same die and the first time a GPU had ever been manufactured on a Silicon-on-Insulator (SOI) substrate. However, we made several organizational and operational changes in the second half of the year that led to a dramatic increase in production velocity and major breakthroughs in yield learning. Now we have not only met all of AMD’s 32nm product shipment requirements, but we have exceeded them.

In fact, our calculations show that the 32nm ramp has actually outpaced the 45nm ramp by a significant margin. Cumulative die shipments for the first five quarters of wafer production are more than double that achieved during the same period of the 45nm technology ramp, despite the integration of a number of new and complex elements at 32nm.

And the good news does not end there. Since our 28nm technology uses the same HKMG implementation as 32nm, AMD and many other 28nm customers will benefit greatly from the learning we have achieved during the high-volume ramp at 32nm. Our 28nm HKMG technology is qualified and ready for design-in today. We began running our first 28nm customer products in Q4 2011 and we have multiple more planned for 2012. 2011 was clearly a year of transformation for GLOBALFOUNDRIES, but we have gained a tremendous amount of momentum and we are starting off 2012 on the right foot.