Application-specific integrated circuits (ASICs) have always offered chip designers the most unique way to fully exercise chip-level differentiation. As development costs at the leading edge rise, the lifetime revenue associated with each ASIC also rises. This presents the need for sustained investment on the part of the ASIC vendor and a continued close partnership between the customer and the ASIC vendor.
Today, GLOBALFOUNDRIES’ ASIC FX-14 offering combines this rich legacy of ASIC expertise with manufacturing scale and process technology leadership to deliver the design and development of ASICs for cloud, data center, and wired and wireless infrastructure applications. Not only does the offering use our qualified 14LPP process technology, but it also brings added value with an optimized IP portfolio to enable chip design. An important piece of IP in the FX-14 offering is the High Speed Serdes (HSS) solution, which is vital for the development of networking ASICs, supporting chip to chip, chip to module, and backplane communications. In addition to the 30G capability to drive backplane, chip to chip and very short reach applications, we have added 56G Serdes capability to be used by customers in their ASIC designs.
Nowadays, it’s all about getting more performance to meet the needs within a power budget. In fact, what it comes down to is how much we can pack into a design and how can we get it in to a “low power” operation. Now, through access to the 14LPP technology, we are able to make dramatic reductions in area and power, as well as increases in performance, enabling us to target next-generation networking applications and meet challenging power consumption demands. FX-14 extends well into high-performance computing applications, with a sweet spot around the wired/wireless infrastructure, and the opportunity to extend into lower end applications.
With the FX-14 offering we have licensed a set of leading-edge ARM cores, including 64-bit ARM processors, for use in highly-advanced communications ASICs. With the addition of the ARM’s cores and peripherals, our customers will now have the broadest array of leading silicon technology and design services available – giving them the ability to create the next generation of communications hardware.
With 15 years of ternary content-addressable memory (TCAM) design experience and the fastest TCAM in the industry, FX-14 is capable of billions of searches per second as well as extremely well optimized for high density and low power. Through the 14LPP process technology, we have access to the industry’s smallest memory cell to achieve outstanding SRAM density as well as take advantage of a performance-tuned memory cell to achieve the best-in-class performance.
The FX-14 ASIC Offering also brings along a very rich set of advanced packaging capabilities. Over and above the always present wire bond and flip chip capabilities, now customers can exercise their creativity by implementing the chips using 3D as well as 2.5D packaging techniques. IBM Microelectronics had a rich history of 3D packaging and GLOBALFOUNDRIES has had several years of investment around 2.5D packaging technologies.
As GLOBALFOUNDRIES moves beyond the 14nm process node we will continue to leverage those technologies as we build up the ASIC offering on top.
For those of us who have been in this business for a while, the divestment of IBM’s Microelectronics Group to GLOBALFOUNDRIES created a tremendous opportunity. Post-acquisition, we have been integrated as a business unit, are leveraging the best-in-class process node roadmap from GLOBALFOUNDRIES, have significantly increased our engagement points with our target customers by having the right solution set of IP blocks, and have the continued expertise to partner with our customers on their next generation ASIC designs.
Not that we ever left the game, but we’re really excited about the new wind behind our sail!
Aashish Malhotra is the Director of ASIC Business Development and Offering at GLOBALFOUNDRIES with responsibility for defining GLOBALFOUNDRIES’ ASIC solution offering in the target markets and manages the associated design wins and margin extraction. He began his career as an ASIC designer at LSI Logic and had held a variety of roles in the semiconductor industry with increasing levels of responsibilities. He holds an MBA from Santa Clara University and an MS in Electrical Engineering from University of Cincinnati.