GLOBALFOUNDRIES Announces Agreement with Singapore’s Institute of Microelectronics and Masdar Institute of Science and Technology of Abu Dhabi for Twin Lab

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GLOBALFOUNDRIES signed a MOU with Singapore’s Institute of Microelectronics (IME) and Masdar Institute of Science and Technology of Abu Dhabi on Tuesday, Nov. 26, to set up an Abu Dhabi-Singapore Twin Lab. The Twin Lab will aim to advance electro-mechanical systems (MEMS) technologies for automotive, aerospace, consumer, healthcare, environmental monitoring, industrial and mobility applications.

The announcement was made at the 7th convening of the Abu Dhabi-Singapore Joint Forum (ADJSF) hosted in Singapore at the Marina Bay Sands Expo Convention Centre. The total funding pledged was US $21 million for three years.

The Twin Lab is a unique collaborative effort between research institutions and industry with GLOBALFOUNDRIES as the industrial partner. GLOBALFOUNDRIES will serve as an overall program manager, as well as manufacturing partner for the Twin Lab. The partnership will help GLOBALFOUNDRIES to expand its IP portfolio to address MEMS high-volume manufacturing at effective cost levels and capacity to serve the fast growing MEMS market.

As the academic partner, Abu Dhabi’s Masdar Institute will develop device designs based on market requirements and the Institute of Microelectronics Singapore will serve as the research institute for the execution of design concepts. GLOBALFOUNDRIES will work closely with ATIC and EDB to bring these concepts into realization.

The initial areas of focus for the Twin Lab will include MEMS inertial sensors, energy harvesters, nano-opto-mechanical sensors, and ultrasonic transducers. The collaboration is intended to deliver capabilities that can mitigate power issues in high performance devices, such as automobile, industrial and autonomous wireless sensor nodes. It is also expected to improve sensitivity and accuracy for effective detection in healthcare, aerospace and industry applications.

 “We are pleased to be in a strategic and mutually beneficial collaboration with the renowned research institutes from Singapore and Abu Dhabi,” said Mr. K. C. Ang, Senior Vice President and General Manager of GLOBALFOUNDRIES Singapore. “This joint partnership will enable us to harness their R&D capabilities to create innovative technologies that will further solidify and strengthen our foundation in MEMS manufacturing.” 

The Mobile Revolution: Taking it to the Next Level

By Srinivas Nori

Today our friends at ARM announced the launch of their newest processor targeted at the rapidly growing market for mid-range mobile devices. The ARM Cortex-A12 processor is expected to offer a significant performance uplift and direct upgrade path from the highly successful Cortex-A9 processor, while matching the energy-efficiency of its predecessor.

Most of the attention these days goes to the latest and greatest high-end superphones and tablets—and of course ARM has processors to serve this important segment—but the market for entry-level and mid-range smartphones is where the real growth is expected to occur in the coming years. For example, a recent report by ABI research projected that shipments of sub-$250 smartphones will grow from 259 million units in 2013 to 788 million units in 2018, at which point they will make up nearly half (46%) of the global smartphone market.

What do consumers want in an entry-level smartphone? They expect similar levels of performance and battery life as enabled by application processors for high-end smartphones, but in a more cost-effective system. Delivering this functionality is no small challenge, and it requires a tight partnership between SoC design and process technology to optimize performance, power, and cost.

ARM_GF_Timeline
Timeline of GLOBALFOUNDRIES and ARM’s relationship

We have been collaborating for years to optimize ARM processors for GLOBALFOUNDRIES leading-edge process technology. Today, in conjunction with the launch of the Cortex-A12 processor, we announced new power, performance and cost optimized POP™ IP technology offerings for the ARM Cortex-A12 and ARM Cortex-A7 processors for our 28nm-SLP High-K Metal Gate (HKMG) process technology. You can read more here about this latest milestone in our multi-year collaboration with ARM. The upshot is that this combination of ARM’s processor IP and our leading-edge process technology will enable a new level of system performance and power efficiency with the optimum economics necessary to serve the market for mid-range mobile devices. GLOBALFOUNDRIES’ 28nm-SLP process technology and associated ARM POP IP for the Cortex-A12 processor enables up to 70 percent higher performance (measured single-thread performance) and up to 2x better power efficiency in comparison to a Cortex-A9 processor using 40nm process technology. Designers can achieve even higher performance by trading off for lower power efficiency, depending on their application needs.

But of course the technology industry continues its relentless march forward, and we have no plans to stop there. We are already collaborating to optimize ARM processor IP for our next-generation 14nm-XM technology. Our 14 nm-XM offering is based on a modular technology architecture that uses a 14nm FinFET device combined with elements of GLOBALFOUNDRIES’ proven 20 nm-LPM process, which will give SoC designers the benefits of FinFET technology with reduced risk and time-to-market. The XM stands for “eXtreme Mobility,” and it is truly optimized for mobile SoC designs.

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14XM Dual-Core Cortex-A9 PPA Proof Point. Similar results are expected for Cortex-A12

Back in February at the Common Platform Technology Forum, we announced results from the industry’s first implementation of a dual-core ARM® Cortex™-A9 processor using FinFET transistors. We found the following results for a Cortex-A9 processor implemented on 14nm-XM technology. Similar results are expected for Cortex-A12 processor implementations.

Here are the technical details:

  • High-performance, energy-efficient ARM processors implemented on 28nm-SLP typically use 12-track libraries. However at 14nm-XM FinFET technology, much higher performance and more energy-efficient ARM processors can be implemented using 9-track libraries resulting in further die-size reductions.
  • At constant power, the frequency achieved with 14nm-XM technology based implementation (using 9-track libraries) is expected to be 61% faster than the frequency achieved with 28nm-SLP technology based implementation (using 12-track libraries).
  • At constant frequency, the power consumed by 14nm-XM technology based implementation is expected to be 62% lower than the power consumed by 28nm-SLP technology based implementation.
  • The performance-power efficiency of 14nm-XM technology based implementation (expressed as DMIPs/milliwatts) is anticipated to be more than twice that of the 28nm-SLP technology based implementation, while using half the silicon area.

The mobile revolution has only just begun. We are excited to see where this dynamic industry will go next, and you can be sure we will continue collaborating with innovative partners like ARM to bring the next generation of connected devices to life.

Srinivas Nori is director, SoC innovation at GLOBALFOUNDRIES. In this role Srinivas owns the GLOBALFOUNDRIES strategy and realization for ARM ecosystem based solutions. Srinivas also oversees the exploration, identification, evaluation and collaborative offering of innovative SoC solutions.

GLOBALFOUNDRIES to Highlight Technology Innovation at DAC 2013

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GLOBALFOUNDRIES is ramping up for the Design Automation Conference (DAC) this summer! During the event, which runs from June 3-6 in Austin, Texas, GLOBALFOUNDRIES will be featuring the latest details on its mainstream and leading-edge technology solutions and roadmap.  

GLOBALFOUNDRIES will be located at booth #1314 at DAC 13 for the duration of the event. In addition to highlighting our new 14nm-XM FinFET technology that will deliver more than twice the energy efficiency of a 28nm-SLP technology-based design, we’ll be demonstrating several products, including:

  • 20nm/14XM solutions; 28nm design methodology (Analog and Digital)
  • 28nm Super Low Power (SLP) Technology with Gate First HKMG, the optimized solution for high performance mobile applications, fully enabled today with design kits and IP
  • GlobalShuttle, the Multi Project Wafer program for product prototyping, device characterization, IP validation and design enablement
  • RF CMOS and other value added solution process modules
  • DFM; analog and digital reference flows; process-specific applications

GLOBALFOUNDRIES will also host a series of one-hour private technical seminars daily, which  will touch on a variety of topics, from our collaborative work with ARM to produce smartphones on our 28nm-SLP HKMG process to parasitic challenges for FinFET designs and analog mixed signal flows and methodology for double patterning and FinFETs. Pre-registration will be required for these informative seminars.

In addition to the seminars, a number of presentations and theater presentations will be given throughout the week including:

Tuesday, June 4

  • Pavilion Panel, Dave McCann: Is This the Right Time to Create Standards for 2.5D/3D-IC Designs?
  • Synopsys Breakfast, Subi Kengeri and Kelvin Low: Ready for Deploying 14XM FinFETs in Your Next Mobile SoC Design Management Day, Bob Madge: Decision-Making for Complex ICs
  • Cadence IP Talks, Subi Kengeri: Enabling SoC level differentiation through advanced technology R&D

Wednesday, June 5

  • Mentor Panel, Richard Trihy, No Fear of FinFET
  • Pavilion Panel, Luigi Capodieci, Learn the Secrets of Design for Yield

For more information and to schedule meetings at the show, check out our DAC microsite.  

Reshaping the Foundry Industry: Welcome to Foundry 2.0

CEO Ajit Manocha lays out winning strategy for nation’s comeback at Nikkei Electronics’ World Semiconductor Summit

GLOBALFOUNDRIES CEO Ajit Manocha spoke to a crowd of more than 200 high-ranking executives from the Japanese semiconductor industry last week at the Nikkei Electronics’ World Semiconductor Industry Summit 2013 in Tokyo. During Manocha’s presentation titled, “Reshaping the Foundry Industry: Welcome to Foundry 2.0,” he outlined the evolution and future of the foundry model, the technical and business drivers reshaping the landscape and what it will take for Japanese IDM companies to move forward. Manocha urged Japanese companies to embrace the fabless model and revise their perspective on previous paradigms.

GLOBALFOUNDRIES is committed to the idea that future success in the semiconductor industry is dependent on joint development at the technology definition level, early engagement at the architectural stage and leveraging a more integrated and cooperative ecosystem. The same theme was very present in Manocha’s speech as he emphasized that the idea that Japan’s resurgence into the semiconductor industry can be fueled collaborative device partnerships.

GLOBALFOUNDRIES recently demonstrated its commitment to collaboration at The Common Platform Technology Forum 2013, where we made a number of joint announcements with our partners. Among those collaborations include Rambus, Synopsys, Adapteva and Cyclos Semiconductor – all of which will mutually benefit GLOBALFOUNDRIES and our partners, but more importantly our customers.

You can watch Manocha’s full speech online on our YouTube channel. Important highlights include:

  • The old foundry model will no longer work with due to a slower rate of change, and inflexible methods and systems which are now required to become flexible (23:33)
  • Our vision for 2020 includes homogeneous alliances as well as heterogeneous alliances between foundries, the airline industry, banking industry, semiconductors and the biomedical field (24:53)
  • GLOBALFOUNDRIES’ acceleration of growth, viewed as a timeline (31:36):
    • From 2007 to 2012, we developed the 65-, 45-, 32- and 28nm designs
    • From 2013 to 2017, we have plans to break into the 20-, 14-, 10- and finally the 7nm design

Common Technology, Uncommon Solutions

common platformBy Mike Noonen

Collaboration has become a well-worn buzzword in our industry in recent years, and for good reason. The scale and complexity of the challenges we collectively face can only be addressed by working together across the entire semiconductor ecosystem. But while many companies are just giving lip service to the concept of collaboration, it has been a part of our DNA at GLOBALFOUNDRIES since our inception.

One of our most important partnerships is in the form of the Common Platform alliance, a groundbreaking collaboration with IBM and Samsung—two of the world’s foremost technology companies—to address the needs of semiconductor manufacturing by providing access to leading-edge CMOS process technologies and extensive enablement support and services. Together we are continuing to redefine the landscape of the semiconductor industry, and the fruits of this partnership will be on display next week at the 2013 Common Platform Technology Forum, which will be held on Tuesday, February 5 at the Santa Clara Convention Center.

The theme of this year’s forum is “Real Collaboration = Big Business.” While we will still be providing a deep look into the underlying technologies offered by the alliance, we also want to demonstrate the impressive business momentum that’s been achieved as a byproduct of this collaboration. 2012 was a particularly strong year, with members of the Common Platform seeing significant growth and taking over both the #2 and #3 spots in the worldwide foundry rankings. Research firm IC Insights recently released its projections for the top 20 leading semiconductor suppliers in 2012, and GLOBALFOUNDRIES jumped six spots to break into the top 20 for the first time. IC Insights projected our 2012 revenue to grow 31% over 2011, which would make us the fastest growing semiconductor company in the world. Similarly, IC Insights’ 2012 foundry rankings saw Samsung make a rapid rise to #3 in the foundry, with a near doubling of foundry revenue for two years in a row.

The forum also will showcase the latest technological advances being delivered to the world’s leading electronics companies. Attendees will see and hear firsthand how the combined expertise of our partners is addressing the most demanding IC design and manufacturing challenges. Our collaborative research and innovative technology development have resulted in an accelerated roadmap and rapid customer adoption, and we’ll touch upon these key highlights:

  • Leading-edge process technologies at 32/28-, 20-, 14-nanometer, and beyond
  • Advanced innovations such as FinFet, design & technology co-optimization, and double patterning
  • A peek into the future of next-generation device innovations being researched: silicon nanowires, carbon nanotubes, and 3D device structures
  • A showcase of our ecosystem partners and Common Platform design, enablement, and implementation offerings in our Partner Pavilion

During the morning session, attendees will have the opportunity to hear keynotes from senior leaders at IBM, Samsung, and GLOBALFOUNDRIES, as well as a special keynote from Dr. Dipesh Patel, Executive Vice President and General Manager of the Physical IP Division at ARM. Dr. Patel will talk about the importance of “partnering for innovation to drive diversity.” Mobile computing is fueling the market demand for diversity, innovation, and expansion of the semiconductor industry, but the challenges being faced by system and SoC designers to meet these requirements in terms of performance, power efficiency, and time-to-market continue to grow in light of advanced manufacturing technologies. Dr. Patel will discuss the importance of a strong ecosystem to deliver the right product on time for commercial success, and why “Real Collaboration” on advanced process technology is a necessary and critical ingredient to address these challenges.

If you aren’t able to attend Tuesday’s event in person, please consider tuning in online via the live webcast, which will also be archived after the event. Details can be found at this link: http://www.commonplatform.com/tf2013

Mike Noonen is Executive Vice President, Worldwide Marketing and Sales, for GLOBALFOUNDRIES. In this role, he is responsible for global customer relationships as well as all marketing, sales, customer engineering and quality functions.

GLOBALFOUNDRIES’ Alexie Lee Recognized for Excellence in Manufacturing

Earlier this week, the Manufacturing Institute, the Society of Manufacturing Engineers, University of Phoenix and Deloitte named GLOBALFOUNDRIES’ Alexie Lee one of the first recipients of their Women in Manufacturing STEP (Science, Technology, Engineering and Production) Awards. Honoring women who have demonstrated excellence and leadership in their careers, the announcement highlights Alexie’s achievements in manufacturing through her positive impact on both GLOBALFOUNDRIES and the industry as a whole.

Alexie Lee

In her role as General Counsel and Executive Vice President of Legal and Corporate Affairs, Alexie is responsible for litigation, intellectual property and corporate matters. Additionally, Alexie oversees worldwide corporate communications, government relations and corporate risk management and sustainability, while providing direction and counsel to the CEO, the Board of Directors and other top corporate leaders. GLOBALFOUDRIES’ growth from a one-facility operation to a company with 7 production facilities worldwide can be attributed in part to her actions and strong understanding of the importance of manufacturing to the entire economy. She adds, “I am excited about being involved in the most advanced of advanced manufacturing.  Not only is our industry vital to our nation’s strength, our products drive improvements, at times dramatic, in all our lives.”

GLOBALFOUNDRIES CEO, Ajit Manocha said, “Since helping to launch GLOBALFOUNDRIES in 2009, Alexie has exhibited a tremendous track record of execution and collaboration, helping to propel our company as one of the fastest-growing semiconductor companies in the world. Her leadership is helping GLOBALFOUNDRIES create thousands of new advanced manufacturing jobs in the U.S., and expand the high-tech manufacturing capabilities that will continue to pave the way for long-term economic growth in the U.S. We thank Alexie for her hard work and dedication and we are so proud to see her recognized with this prestigious award.”

The STEP Ahead initiative was launched to examine and promote the role of women in the manufacturing industry through recognition, research and best practices for attracting, advancing, and retaining strong female talent. A total of 122 women were honored this first year, representing a variety of companies at all levels of their manufacturing organization from the factory floor to the C-suite. Award organizers hope that by telling the stories of these women, they can help inspire the next-generation of talent to pursue careers in the industry.  The STEP Awards are also meant to empower honorees to lead in their companies, communities and networks on the importance of manufacturing and issues related to attracting, advancing and retaining strong manufacturing talent.

“The STEP Ahead initiative was founded to change perceptions of the manufacturing industry and create new opportunities for women in the sector,” said Latondra Newton, group vice president at Toyota Motor North America, Inc. and chairwoman of the STEP Ahead initiative. “This initiative is the call for action to transform the face of today’s manufacturing talent and ensure that women can contribute to the future of this industry.”

On February 5th, Alexie will join the other award recipients for a reception in Washington, D.C. where the STEP Awards program will highlight each honoree’s story, including their leadership and accomplishments in manufacturing.

Innovation in Design Rules Verification Keeps Scaling on Track

By Mojy Chian

There is an interesting dynamic that occurs in the semiconductor industry when we talk about process evolution, roadmaps and generally attempt to peer into the future. First, we routinely scare ourselves by declaring that scaling can’t continue and that Moore’s Law is dead (a declaration that has happened more often than the famously exaggerated rumors of Mark Twain’s death). Then, we unfailingly impress ourselves by coming up with solutions and workarounds to the show-stopping challenge of the day. Indeed, there has been a remarkable and consistent track record of innovation to keep things on track, even when it appears the end is surely upon us.

But this time we are really serious – at 20nm, the end is near! Ok, maybe not THE end, but for sure there are some obvious things that need to change if we are to keep our record of continuous technical conquest intact. And, as with most things in this era, collaboration is the key.

Mojy Chian explains the role DFM has in keeping scaling on track.

Sure there are lots of really innovative approaches and exotic technologies being bandied about that hold the potential to keep Moore’s Law chugging along well into the future. But ironically, it’s something of an ‘old’ technology that holds significant potential to address the current issues. Design for manufacturing (DFM) has been around for a long time, most typically as a design-enabling tool delivered by EDA companies to help IC designers understand and deal with manufacturers’ geometrical design rules.  This obviously requires close interaction with the EDA people and the foundries so that design rules are accurate and practical. Literally, these are tools that guide designers with a set of geometrical constraints, necessary to guarantee yield, defined over polygonal shapes and edges in the layout. Traditionally, these design rules are binary – this works, this does not.

But something funny happened on our way past 28nm. The Y word – yield – started becoming one of the, if not the, most important factor in successful IC design. This is because of the intrinsic relationship between yield and the complexity of physical design (and the associated challenges of process-related effects).

In the past, a designer only had two primary options for identifying DFM issues: run accurate but computationally intensive simulations based on numerical algorithms, or rely on metrology measurements directly from the fab. Attempts have been made to improve upon standard DRC with additional rules, but these approaches have had mixed success. For example, some have proposed the use of restrictive design rules that only allow highly regular structures for layout, avoiding problematic two-dimensional geometries altogether. The potential drawback is that designers cannot effectively optimize their circuits to meet application requirements with overly constrained design rules.

So the manufacturers got back together with the EDA suppliers and thought about how to solve the problem. “We need to build on what we have achieved with DRC,” we agreed. “We need more.” So in our infinite wisdom, we came up with something called DRC+. The lack of creativity in the name, however, belies the innovation behind it, which is backed by several patents and reinforces the fact that GLOBALFOUNDRIES innovates in ways beyond just manufacturing process technology.

The concept we are moving towards is the reduction in the number of trade-off decisions a designer needs to make. By providing a tool that will notify the user if a forbidden shape has been used, the designer can be guided more efficiently. In addition, things need to be visually intuitive –  a picture is worth of a thousand words, even in IC design. Such a solution requires tight collaboration between the foundry, which supplies a library of yield critical patterns; EDA providers, which supply ultra-fast pattern-matching tools; and the IC design community itself which provides valuable input on design methodologies and real-world needs.

Pattern-based methodology takes hold

In a nutshell. DFM and design rule checking need to move to a pattern-based approach to provide more visibility into variability issues. Traditional DRC is shape and edge proximity based.  On top of that, we need 2D shape-based pattern-matching physical verification.

As a result, our DRC+ takes a different approach than earlier generations of DRC. Instead of restricting the flexibility of designers, the technique augments standard DRC by applying rapid two-dimensional shape-based pattern matching to identify problematic configurations that could be difficult to manufacture.

Our DRC+ platform includes a silicon verified library of “bad” patterns in a database which can be identified quickly in layout, allowing the designer to fix them. This is an on-going incremental process rather than just occurring at the end of the complete design cycle.

Thus, pattern matching with DRC+ introduces process-awareness earlier in the design process, a concept that is at the basis of the collaborative DFM platform from GLOBALFOUNDRIES.

Two rule-based flows are also part of our DFM platform. The first is yield analysis and scoring, in the form of an equation-based tool to help designers quickly analyze their design for usage of recommended rules, and prioritize fixes for the highest impact violations. The second is an automated yield enhancement “layout-fix” application, which applies recommendations without impacting overall design area.

The net result is improved variability management without sacrifices in design performance or significant impact on design productivity (DRC+ is over 10,000 times faster than printability simulation, and its detection and fixing adds very little to the overall routing runtime).

DFM is something of a broad catch-all term for a number of steps and issues involved ensuring a complex IC design can be manufactured and done in a way that is cost-effective and timely. Design rule checking is just one aspect of it, but a critical one for sure. We are proud of the innovation GLOBALFOUNDRIES continues to demonstrate in many areas, including design enablement technologies like our DRC+. In future posts I’ll explore other ideas for improving how manufacturing issues can be brought more tightly into the design process, including a concept we call Design Enabled Manufacturing (DEM). Stay tuned.

Mojy Chian is senior vice president, design enablement at GLOBALFOUNDRIES. He is responsible for global design enablement, services, and solutions and is the primary technical customer interface for the company.